SK hynix and Sandisk Release an HBF Specification, With Adoption Still to Prove
SK hynix and Sandisk say they have published the first Open Compute Project specification for High Bandwidth Flash, a NAND-based layer intended to sit alongside HBM and SSDs in AI inference systems. The document fixes a technical starting point, but not the performance, cost or hardware support that would make HBF a deployed memory tier.
- The companies have published a common HBF specification through the Open Compute Project rather than a shipping product announcement.
- HBF is proposed as a NAND-based tier that coexists with HBM and SSDs for AI inference systems.
- The specification defines capacity and bandwidth ranges; it does not supply workload benchmarks, prices or deployment commitments.
SK hynix and Sandisk have published what they describe as the first technical specification for High Bandwidth Flash, or HBF, through the Open Compute Project (OCP). SK hynix is a Korean supplier of DRAM and NAND flash, while Sandisk is a Nasdaq-listed flash-memory company. Their announcement places HBF between high-bandwidth memory (HBM) and solid-state drives in a proposed AI-inference memory hierarchy.
The significant change is the move from a joint concept to published design rules. It is not yet evidence that the new tier is faster, cheaper or easier to deploy than established memory-and-storage configurations. The companies' releases identify no shipping HBF devices, compatible host products, application benchmarks, pricing or customer deployment commitments.

SK hynix’s illustration for its announcement of an HBF technical specification with Sandisk through the Open Compute Project. Source: SK hynix Newsroom.
A specification for a proposed third tier
HBM is placed close to processors for very high-speed access, while SSDs offer large storage capacity farther from the compute path. HBF is the companies' attempt to make a NAND-based layer available between them: more capacity near compute than HBM alone, while aiming for more bandwidth than ordinary storage. That is a design objective, not a demonstrated system result.
The published framework covers a host interface between an xPU and HBF, electrical requirements, reliability and packaging guidance for the die stack, and software guidance for reads and writes. It defines two NAND-stack configurations—8-high and 16-high—with capacity up to 512GB. Its three bandwidth grades span approximately 0.4TB/s to 3.0TB/s, according to the report.
The specification adopts Universal Chiplet Interconnect Express, or UCIe, an open interface for high-speed connections among heterogeneous semiconductor chiplets. SK hynix says that choice is intended to let HBF work with different processor types, including GPUs and CPUs. The interface can make integration possible across architectures; it does not settle the latency, endurance, software or packaging trade-offs a system maker would face.
