DFSX’s 15 TB/s chip roadmap still has to clear the production test

Wei has made the limitation unusually explicit. In his comments to reporters, he said 3D stacking is only one route to near-memory computing, not a complete solution. He also gave the basic yield arithmetic: two layers that each yield 90% produce an 81% combined yield. More layers can therefore intensify cost pressure, while process technology remains the ultimate performance ceiling, he said.

Company-reported DFSX roadmap bandwidth alongside the reported NVIDIA GB200 NVL72 system figure; these are aggregate specifications, not application benchmarks. Source: Wccftech.

The NVIDIA comparison is a scope check, not a benchmark

The headline comparison is based on two whole-system configurations with different accelerator counts. DFSX’s stated TY64 configuration uses 64 DF2000 accelerators; the cited NVIDIA GB200 NVL72 configuration uses 72 GPUs. The figures below are peak or aggregate specifications reported for those configurations, not equivalent application tests.

On the reported bandwidth inputs, 960 TB/s is 1.67 times 576 TB/s, or about 67% higher. Calling it “2x” overstates the arithmetic. The same comparison also assigns the GB200 system more than five times the stated BF16 peak compute. Neither side of that contrast demonstrates end-to-end performance on a named model, and the retained reporting provides no independent DF2000 benchmark.

That does not make bandwidth irrelevant. It means the comparison establishes the scale of DFSX’s design target, while leaving open which workload would benefit, whether its software can expose that benefit and what trade-off it makes in energy and deployment economics.

A system sale, backed by a young company

DFSX is not presenting only a chip. In its launch coverage, the company announced an OAM2.0 accelerator card, an eight-card server, a liquid-cooled 64-card TY64 supernode rated at 33 PFLOPS, and an HS128 computing cluster aimed at large-scale training and inference. It says its DF1000 supply chain—from wafer fabrication and packaging through servers and clusters—is domestic. That makes the roadmap a proposition about a locally sourced system stack as well as a processor architecture.

The company was founded in May 2024, is headquartered in Shanghai’s Zhangjiang district and says it has more than 500 people. Its vice president, Guo Wei, said DF2000 would target a doubling of DF1000’s specifications in late 2026, followed by another doubling for DF3000 in the fourth quarter of 2027. Those are internal roadmap goals, not an announced customer deployment.

The financing gives DFSX resources to pursue that plan but does not prove it can fund volume production. The report, citing Securities Times, said the company reached an RMB 12.3 billion valuation after its April 2026 Series A+ round and named the National AI Industry Investment Fund, along with investment funds affiliated with Meituan, Xiaomi and Didi, as backers. Separately, Jiemian reported a more precise RMB 12.275 billion post-money valuation and a planned fourth-quarter Series B round.

The timing helps explain the attention. A report citing IDC put China’s 2025 AI-accelerator shipments at about 4 million units, with local suppliers accounting for 1.65 million, or 41%, while NVIDIA’s share fell from about 70% in 2024 to 55%. Those are secondhand market estimates, not a dataset published in the retained material, but they describe a market in which a domestic full-stack supplier has a clear incentive to prove it can ship at scale.

What would settle the DF2000 claim

The next decision point is not another architecture diagram or a higher bandwidth target. DFSX needs to show DF2000 availability, memory capacity, power use, pricing, manufacturing yield and software support, then publish reproducible results on specified training and inference workloads.

Until then, the evidence supports a more limited conclusion: DFSX has set out a technically distinct route for reducing dependence on advanced nodes and HBM, and its own leadership acknowledges the manufacturing constraint embedded in that route. Whether that trade-off produces a competitive system will be decided by shipped hardware and comparable workloads, not aggregate specifications alone.